View MPC8260ED_320995.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Advance Information
MPC8260EC/D Rev. 1.1 05/2002 MPC8260 (HiP3) Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the HiP3 version of the PowerQUICC IITM MPC8260 communications processor . The following topics are addressed: Topic Section 1.1, "Features" Section 1.2, "Electrical and Thermal Characteristics" Section 1.2.1, "DC Electrical Characteristics" Section 1.2.2, "Thermal Characteristics" Section 1.2.3, "Power Considerations" Section 1.2.4, "AC Electrical Characteristics" Section 1.3, "Clock Configuration Modes" Section 1.3.1, "Local Bus Mode" Section 1.4, "Pinout" Section 1.5, "Package Description" Section 1.6, "Ordering Information" Page 2 5 5 9 9 10 17 17 20 33 35
Features
Figure 1 shows the block diagram for the MPC8260.
16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-Local Bridge Memory Controller Communication Processor Module (CPM) Clock Counter Timers Parallel I/O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM 2 Virtual IDMAs Interrupt Controller 24 Kbytes Dual-Port RAM Serial DMAs System Functions 60x Bus
Local Bus
32 bits, up to 66 MHz
MCC1
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
Time Slot Assigner Serial Interface
8 TDM Ports
3 MII Ports
2 UTOPIA Ports
Non-Multiplexed I/O
Figure 1. MPC8260 Block Diagram
1.1
*
Features
Dual-issue integer core -- A core version of the EC603e microprocessor -- System core microprocessor supporting frequencies of 133-200 MHz -- Separate 16-Kbyte data and instruction caches: - Four-way set associative - Physically addressed - LRU replacement algorithm -- PowerPC architecture-compliant memory management unit (MMU) -- Common on-chip processor (COP) test interface -- High-performance (4.4-5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz) -- Supports bus snooping for data cache coherency -- Floating-point unit (FPU) Separate power supply for internal logic and for I/O
The major features of the MPC8260 are as follows:
*
2
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Features
*
*
*
*
Separate PLLs for G2 core and for the CPM -- G2 core and CPM can run at different frequencies for power/performance optimization -- Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios -- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus -- Bus supports multiple master designs -- Supports single- and four-beat burst transfers -- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller -- Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus -- Single-master bus, supports external slaves -- Eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller System interface unit (SIU) -- Clock synthesizer -- Reset controller -- Real-time clock (RTC) register -- Periodic interrupt timer -- Hardware bus monitor and software watchdog timer -- IEEE 1149.1 JTAG test access port
*
Twelve-bank memory controller -- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals -- Byte write enables and selectable parity generation -- 32-bit address decodes with programmable bank size -- Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine -- Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) -- Dedicated interface logic for SDRAM
* *
CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) -- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols -- Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller -- Serial DMA channels for receive and transmit on all serial channels -- Parallel I/O registers with open-drain and interrupt capability -- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers -- Three fast communications controllers supporting the following protocols: - 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII)
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
3
Features
- ATM--Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections - Transparent - HDLC--Up to T3 rates (clear channel) -- Two multichannel controllers (MCCs) - Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split into four subgroups of 32 channels each. - Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC -- Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: - Ethernet/IEEE 802.3 CDMA/CS - HDLC/SDLC and HDLC bus - Universal asynchronous receiver transmitter (UART) - Synchronous UART - Binary synchronous (BISYNC) communications - Transparent -- Two serial management controllers (SMCs), identical to those of the MPC860 - Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels - Transparent - UART (low-speed operation) -- One serial peripheral interface identical to the MPC860 SPI -- One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) - Microwire compatible - Multiple-master, single-master, and slave modes -- Up to eight TDM interfaces - Supports two groups of four TDM channels for a total of eight TDMs - 2,048 bytes of SI RAM - Bit or byte resolution - Independent transmit and receive routing, frame synchronization - Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces -- Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels -- Four independent 16-bit timers that can be interconnected as two 32-bit timers
4
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.2
1.2.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8260.
This section describes the DC electrical characteristics for the MPC8260. Table 1 shows the maximum electrical ratings.
Table 1. Absolute Maximum Ratings1
Rating Core supply voltage2 PLL supply I/O supply voltage2 Symbol VDD VCCSYN VDDH VIN Tj TSTG Value -0.3 - 2.75 -0.3 - 2.75 -0.3 - 4.0 GND(-0.3) - 3.6 120 (-55) - (+150) Unit V V V V C C
voltage3
Input voltage4 Junction temperature Storage temperature range
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. 3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.0 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 2 lists recommended operational voltage conditions.
Table 2. Recommended Operating Conditions1
Rating Core supply voltage PLL supply voltage I/O supply voltage Input voltage Junction temperature (maximum)
1
Symbol VDD VCCSYN VDDH VIN Tj
2.5-V Device2 2.4-2.7 2.4-2.7 3.135 - 3.465 GND (-0.3) - 3.465 105
Unit V V V V C
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these conditions is not guaranteed. 2 Parts labeled with an "-HVA" suffix are 2.6-V devices.
NOTE VDDH and VDD must track each other and both must vary in the same direction--in the positive direction (+5% and +0.1 Vdc) or in the negative direction (-5% and -0.1 Vdc).
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
5
Electrical and Thermal Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC). Table 3 shows DC electrical characteristics.
Table 3. DC Electrical Characteristics
Characteristic Input high voltage, all inputs except CLKIN Input low voltage CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH1 = VDDH1 Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH Min 2.0 GND 2.4 GND -- -- -- -- 2.4 Max 3.465 0.8 3.465 0.4 10 10 1 1 -- Unit V V V V A A A A V
Hi-Z (off state) leakage current, VIN Signal low input current, VIL = 0.8 V
Signal high input current, VIH = 2.0 V Output high voltage, IOH = -2 mA except XFC, UTOPIA mode, and open drain pins In UTOPIA mode: IOH = -8.0mA PA[0-31] PB[4-31] PC[0-31] PD[4-31] In UTOPIA mode: IOL = 8.0mA PA[0-31] PB[4-31] PC[0-31] PD[4-31]
VOL
--
0.5
V
6
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics (Continued)
Characteristic IOL = 7.0mA BR BG ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0-3] AACK ARTRY DBG DBB/IRQ3 D[0-63] DP(0)/RSRV/EXT_BR2 DP(1)/IRQ1/EXT_BG2 DP(2)/TLBISYNC/IRQ2/EXT_DBG2 DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/IRQ5/EXT_DBG3 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0/NMI_OUT IRQ7/INT_OUT/APE PORESET HRESET SRESET RSTCONF QREQ Symbol VOL Min -- Max 0.4 Unit V
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
7
Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics (Continued)
Characteristic IOL = 5.3mA CS[0-9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27-28] ALE BCTL0 PWE(0:7)/PSDDQM(0:7)/PBS(0:7) PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0-3]LSDDQM[0:3]/LBS[0-3] LSDA10/LGPL0 LSDWE/LGPL1 LOE/LSDRAS/LGPL2 LSDCAS/LGPL3 LGTA/LUPMWAIT/LGPL4/LPBS LSDAMUX2/LGPL5 LWR MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL(2) IOL = 3.2mA L_A14 L_A15/SMI L_A16 L_A17/CKSTP_OUT L_A18 L_A19 L_A20 L_A21 L_A22 L_A23 L_A24 L_A25 L_A26 L_A27 L_A28/CORE_SRESET L_A29 L_A30 L_A31 LCL_D(0-31) LCL_DP(0-3) PA[0-31] PB[4-31] PC[0-31] PD[4-31] TDO
1
Symbol VOL
Min --
Max 0.4
Unit V
The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction; that is, VDDH and VDD either both vary in the positive direction (+5% and +0.1 Vdc) or both vary in the negative direction (-5% and -0.1 Vdc). 2 Only Rev C.2 silicon.
8
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.2.2
Thermal Characteristics
Table 4. Thermal Characteristics
Characteristics Symbol JA JA JA JA Value 13.071 9.551 10.483 7.783 Unit C/W C/W C/W C/W Air Flow NC2 1 m/s NC 1 m/s
Table 4 describes thermal characteristics.
Thermal resistance for TBGA
1 2
Assumes a single layer board with no thermal vias Natural convection 3 Assumes a four layer board
1.2.3
Power Considerations
TJ = TA + (PD x JA) (1)
The average chip-junction temperature, TJ, in C can be obtained from the following: where TA = ambient temperature C
JA = package thermal resistance, junction to ambient, C/W
PD = PINT + PI/O PINT = IDD x VDD Watts (chip internal power) PI/O = power dissipation on input and output pins (determined by user) For most applications PI/O < 0.3 x PINT. If PI/O is neglected, an approximate relationship between PD and TJ is the following: PD = K/(TJ + 273 C) Solving equations (1) and (2) for K gives: K = PD x (TA + 273 C) + JA x PD2 (3) (2)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
1.2.3.1
Layout Practices
Each VCC pin should be provided with a low-impedance path to the board's power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
9
Electrical and Thermal Characteristics
All output pins on the MPC8260 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required for conditions above PD = 3W (when the ambient temperature is 70 C or greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be included when determining whether to use a heat sink.
Table 5. Estimated Power Dissipation for Various Configurations1
PINT (W)2 Bus (MHz) CPM Multiplier CPU Multiplier CPM (MHz) CPU (MHz) 2.4 33.3 50.0 66.7 66.7 66.7 66.7 50.0
1 2
Vddl 2.5 2.14 2.30 2.62 2.69 2.95 3.05 3.00 2.6 2.26 2.45 2.74 2.83 3.12 3.22 3.14 2.7 2.38 2.59 2.88 2.98 3.29 3.38 3.31 2.83 2.50 2.69 3.02 3.12 3.43 3.55 3.48
4 2 2 2.5 2 2.5 3
4 3 2.5 2.5 3 3 4
133.3 100 133.3 166.7 133.3 166.7 150
133.3 150.0 166.7 166.7 200.0 200.0 200.0
2.04 2.21 2.47 2.57 2.81 2.88 2.83
Test temperature = room temperature (25 C) PINT = IDD x VDD Watts 3 2.8 Vddl does not apply to HiP3 Rev C silicon.
1.2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for the 66 MHz MPC8260 device. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 6.
Table 6. Output Buffer Impedances1
Output Buffers 60x bus Local bus Memory controller Parallel I/O
1
Typical Impedance () 40 40 40 46
These are typical values at 65 C. The impedance may vary by 25% with process and temperature.
10
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Table 7 lists CPM output characteristics.
Table 7. AC Characteristics for CPM Outputs1
Spec_num Max/Min Max Delay (ns) Min Delay (ns) Characteristic 66 MHz 6 14 25 19 19 14 66 MHz 1 2 5 1 2 1
sp36a/sp37a FCC outputs--internal clock (NMSI) sp36b/sp37b FCC outputs--external clock (NMSI) sp40/sp41 TDM outputs/SI
sp38a/sp39a SCC/SMC/SPI/I2C outputs--internal clock (NMSI) sp38b/sp39b Ex_SCC/SMC/SPI/I2C outputs--external clock (NMSI) sp42/sp43
1
PIO/TIMER/DMA outputs
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.
Table 8 lists CPM input characteristics.
Table 8. AC Characteristics for CPM Inputs1
Setup (ns) Hold (ns) Spec_num sp16a/sp17a sp16b/sp17b sp20/sp21 sp18a/sp19a sp18b/sp19b sp22/sp23
1
Characteristic 66 MHz FCC inputs--internal clock (NMSI) FCC inputs--external clock (NMSI) TDM inputs/SI SCC/SMC/SPI/I2C inputs--internal clock (NMSI) SCC/SMC/SPI/I2C inputs--external clock (NMSI) PIO/TIMER/DMA inputs 10 3 15 20 5 10 66 MHz 0 3 12 0 5 3
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge.
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
11
Electrical and Thermal Characteristics
Figure 2 shows the FCC external clock.
Serial ClKin sp17b sp16b FCC input signals sp36b/sp37b FCC output signals
Figure 2. FCC External Clock Diagram
Figure 3 shows the FCC internal clock.
BRG_OUT sp17a sp16a FCC input signals sp36a/sp37a FCC output signals
Figure 3. FCC Internal Clock Diagram
Figure 4 shows the SCC/SMC/SPI/I2C external clock.
Serial CLKin sp19b sp18b SCC/SMC/SPI/I2C input signals sp38b/sp39b SCC/SMC/SPI/I2C output signals
Figure 4. SCC/SMC/SPI/I2C External Clock Diagram
12
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 5 shows the SCC/SMC/SPI/I2C internal clock.
BRG_OUT sp18a SCC/SMC/SPI/I2C input signals sp38a/sp39a SCC/SMC/SPI/I2C output signals sp19a
Figure 5. SCC/SMC/SPI/I2C Internal Clock Diagram
Figure 6 shows PIO, timer, and DMA signals.
CLKin sp23 sp22 PIO/TIMER/DMA input signals sp42/sp43 TIMER/DMA output signals sp42/sp43 PIO output signals
Figure 6. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
Table 9. AC Characteristics for SIU Inputs1
Setup (ns) Hold (ns) Spec_num Characteristic 66 MHz sp11/sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR sp12/sp10 Data bus in normal mode sp13/sp10 Data bus in ECC and PARITY modes sp14/sp10 DP pins sp15/sp10 All other pins
1
66 MHz 1 1 1 1 1
6 5 8 8 5
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
13
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Table 10. AC Characteristics for SIU Outputs1
Spec_num Max/Min Max Delay (ns) Min Delay (ns) Characteristic 66 MHz 10 8 8 12 6 7.5 66 MHz 0.5 0.5 0.5 0.5 0.5 0.5
sp31/sp30 PSDVAL/TEA/TA sp32/sp30 ADD/ADD_atr./BADDR/CI/GBL/WT sp33a/sp30 Data bus sp33b/sp30 DP sp34/sp30 memc signals/ALE sp35/sp30 all other signals
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.
Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. When data pipelining is activated, sp12 can be used for data bus setup even when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP signals. Figure 7 shows TDM input and output signals.
Serial CLKin sp20 TDM input signals sp40/sp41 TDM output signals sp21
Figure 7. TDM Signal Diagram
Figure 8 shows the interaction of several bus signals.
14
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
CLKin sp11 AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals sp12 DATA bus normal mode input signal sp15 All other input signals sp31 PSDVAL/TEA/TA output signals sp32 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals sp33a DATA bus output signals sp30 sp30 sp10 sp10 sp10
sp30
sp35
sp30
All other output signals
Figure 8. Bus Signals
Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin sp10 sp13 DATA bus, ECC, and PARITY mode input signals
sp10 sp14 DP mode input signal
sp33b/sp30 DP mode output signal
Figure 9. Parity Mode Diagram
Figure 10 shows signal behavior in MEMC mode.
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
15
Electrical and Thermal Characteristics
CLKin
V_CLK
Memory controller signals
sp34/sp30
Figure 10. MEMC Mode Diagram
NOTE Generally, all MPC8260 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Ratio T2 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1/4 CLKin 3/10 CLKin 4/14 CLKin T3 1/2 CLKin 1/2 CLKin 1/2 CLKin T4 3/4 CLKin 8/10 CLKin 11/14 CLKin
Figure 11 is a graphical representation of Table 11.
CLKin T1 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin T1 T2 T3 T4
for 1:2.5
CLKin T1 T2 T3 T4
for 1:3.5
Figure 11. Internal Tick Spacing for Memory Controller Signals
NOTE The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin's rising edge.
16
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Clock Configuration Modes
1.3
Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the MODCK[1-3] pins are sampled while HRESET is asserted. Table 12 shows the eight basic configuration modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
1.3.1
Local Bus Mode
Table 12. Clock Default Modes
Table 12 describes default clock modes for the MPC8260.
MODCK[1-3] 000 001 010 011 100 101 110 111
Input Clock Frequency 33 MHz 33 MHz 33 MHz 33 MHz 66 MHz 66 MHz 66 MHz 66 MHz
CPM Multiplication Factor 3 3 4 4 2 2 2.5 2.5
CPM Frequency 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz
Core Multiplication Factor 4 5 4 5 2.5 3 2.5 3
Core Frequency 133 MHz 166 MHz 133 MHz 166 MHz 166 MHz 200 MHz 166 MHz 200 MHz
Table 13 describes all possible clock configurations when using the hard reset configuration sequence. Note that clock configuration changes only after POR is asserted. Note also that basic modes are shown in boldface type.
Table 13. Clock Configuration Modes1
MODCK_H-MODCK[1-3] 0001_000 0001_001 0001_010 0001_011 0001_100 Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 2 2 2 2 2 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 4 5 6 7 8 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0001_101 0001_110 0001_111 0010_000 0010_001
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
3 3 3 3 3
100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
17
Clock Configuration Modes Table 13. Clock Configuration Modes1 (Continued)
MODCK_H-MODCK[1-3] 0010_010 0010_011 0010_100 0010_101 0010_110 Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 4 4 4 4 4 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 4 5 6 7 8 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0010_111 0011_000 0011_001 0011_010 0011_011
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
5 5 5 5 5
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0011_100 0011_101 0011_110 0011_111 0100_000
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
6 6 6 6 6
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0100_001 0100_010 0100_011 0100_100 0100_101 0100_110 0100_111 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 0101_110 0101_111 0110_000 0110_001 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 2 2 2 2 2
Reserved
Reserved
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
2 2.5 3 3.5 4
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
18
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 13. Clock Configuration Modes1 (Continued)
MODCK_H-MODCK[1-3] 0110_010 Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2 66 MHz 2 133 MHz 4.5 300 MHz
0110_011 0110_100 0110_101 0110_110 0110_111 0111_000
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
2.5 2.5 2.5 2.5 2.5 2.5
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
0111_001 0111_010 0111_011 0111_100 0111_101 0111_110
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
3 3 3 3 3 3
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
0111_111 1000_000 1000_001 1000_010 1000_011 1000_100
1 2
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
3.5 3.5 3.5 3.5 3.5 3.5
233 MHz 233 MHz 233 MHz 233 MHz 233 MHz 233 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
Because of speed dependencies, not all of the possible configurations in Table 13 are applicable. The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU ranges between 133-200and the CPM ranges between 50-166 MHz. 3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H-MODCK_L so that the resulting configuration does not exceed the frequency rating of the user's part. Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 66 MHz input clock and MODCK_H-MODCK_L[0111-101] (with a core multiplication factor of 4 and a CPM multiplication factor of 3). The resulting configuration equals the part's maximum possible frequencies of 266 MHz CPU, 200 MHz CPM, and 66 MHz bus. 2. 50 MHz input clock and MODCK_H-MODCK_L[0111-101] to achieve a configuration of 200 MHz CPU, 150 MHz CPM, and 50 MHz bus. 3. 40 MHz input clock and MODCK_H-MODCK_L[0010-011] to achieve a configuration of 200 MHz CPU, 160 MHz CPM, and 40 MHz bus. Note that with each example, any one of several values for MODCK_H-MODCK_L could possibly be used as long as the resulting configuration does not exceed the part's rating.
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
19
Pinout
1.4
1.4.1
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ 1
Pinout
Pin Assignments
2 3 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ 2 3 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
This section provides the pin assignments and pinout list for the MPC8260.
Figure 12 shows the pinout of the MPC8260's 480 TBGA package as viewed from the top surface.
Not to Scale
Figure 12. Pinout of the 480 TBGA Package as Viewed from the Top Surface
Figure 13 shows the side profile of the TBGA package to indicate the direction of the top surface view.
20
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Pinout
View
Copper Heat Spreader (Oxidized for Insulation) Polymide Tape Die Soldermask Glob-Top Filled Area Glob-Top Dam 1.27 mm Pitch Copper Traces Die Attach Etched Cavity Pressure Sensitive Adhesive
Figure 13. Side View of the TBGA Package
Table 14 shows the pinout list of the MPC8260. Table 15 defines conventions and acronyms used in Table 14.
Table 14. Pinout List
Pin Name BR BG ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 W5 F4 E2 E3 G1 H5 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L5 L4 L3 L2 L1 M5 N5 Ball
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
21
Pinout Table 14. Pinout List (Continued)
Pin Name A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 D8 N4 N3 N2 N1 P4 P3 P2 P1 R1 R3 R5 R4 F1 G4 G3 G2 F2 D3 C1 E4 D2 F5 F3 E1 V1 V2 B20 A18 A16 A13 E12 D9 A6 B5 A20 Ball
22
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Pinout Table 14. Pinout List (Continued)
Pin Name D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 E17 B15 B13 A11 E9 B7 B4 D19 D17 D15 C13 B11 A8 A5 C5 C19 C17 C15 D13 C11 B8 A4 E6 E18 B17 A15 A12 D11 C8 E7 A3 D18 A17 A14 B12 Ball
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
23
Pinout Table 14. Pinout List (Continued)
Pin Name D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 A10 D8 B6 C4 C18 E16 B14 C12 B10 A7 C6 D5 B18 B16 E14 D12 C10 E8 D6 C2 B22 A22 E21 D21 C21 B21 A21 E20 V3 C22 V5 W1 U2 U3 Y4 Ball
24
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Pinout Table 14. Pinout List (Continued)
Pin Name CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/ LWE1/LSDDQM1/LBS1/ U4 R2 Y3 F25 C29 E27 E28 F26 F27 F28 G25 D29 E29 F29 G28 T5 U1 T2 A27 C25 E24 D24 C24 B26 A26 B25 A25 E23 B24 A24 B23 A23 D22 H28 H27 Ball
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
25
Pinout Table 14. Pinout List (Continued)
Pin Name LWE2/LSDDQM2/LBS2/ LWE3/LSDDQM3/LBS3/ LSDA10/LGPL0/ LSDWE/LGPL1/ LOE/LSDRAS/LGPL2/ LSDCAS/LGPL3/ LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX1 LWR L_A14 L_A15/SMI L_A16 L_A17/CKSTP_OUT L_A18 L_A19 L_A20 L_A21 L_A22 L_A23 L_A24 L_A25 L_A26 L_A27 L_A28/CORE_SRESET L_A29 L_A30 L_A31 LCL_D0 LCL_D1 LCL_D2 LCL_D3 LCL_D4 LCL_D5 LCL_D6 LCL_D7 H26 G29 D27 C28 E26 D25 C26 B27 D28 N27 T29 R27 R26 R29 R28 W29 P28 N26 AA27 P29 AA26 N25 AA25 AB29 AB28 P25 AB27 H29 J29 J28 J27 J26 J25 K25 L29 Ball
26
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Pinout Table 14. Pinout List (Continued)
Pin Name LCL_D8 LCL_D9 LCL_D10 LCL_D11 LCL_D12 LCL_D13 LCL_D14 LCL_D15 LCL_D16 LCL_D17 LCL_D18 LCL_D19 LCL_D20 LCL_D21 LCL_D22 LCL_D23 LCL_D24 LCL_D25 LCL_D26 LCL_D27 LCL_D28 LCL_D29 LCL_D30 LCL_D31 LCL_DP0 LCL_DP1 LCL_DP2 LCL_DP3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TCK TMS TDI TDO L27 L26 L25 M29 M28 M27 M26 N29 T25 U27 U26 U25 V29 V28 V27 V26 W27 W26 W25 Y29 Y28 Y25 AA29 AA28 L28 N28 T28 W28 T1 D1 AH3 AG5 AJ3 AE6 AF5 Ball
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
27
Pinout Table 14. Pinout List (Continued)
Pin Name TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 XFC CLKIN1 PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2 PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3 PA2/CLK20/FCC2_UTM_TXADDR0/DACK3 PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2 PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4 PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2 PA6/L1RSYNCA1 PA7/SMSYN2/L1TSYNCA1/L1GNTA1 PA8/SMRXD2/L1RXD0A1/L1RXDA1 PA9/SMTXD2/L1TXD0A1 PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11 PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10 AB4 AG6 AH5 AF6 AA3 AJ4 W2 W3 W4 AB2 AH4 AC29 AC25 AE28 AG29 AG28 AG26 AE24 AH25 AF23 AH23 AE22 AH22 AJ21 AH20 AG19 AF18 AF17 AE16 AJ16 AG15 AJ13 AE13 AF12 AG11 Ball
28
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Pinout Table 14. Pinout List (Continued)
Pin Name PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1 PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0 PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2 PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2 PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2 PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3_RXD/TXD3/L1RSYNCD1 PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1 PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1 PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1 PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2 PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1 PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1 PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18 PB17/FCC3_MII_RX_DV/L1RQA1/CLK17 PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1 PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/ L1TXD2A1 PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2 PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2 PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/ FCC2_MII_TX_EN AH9 AJ8 AH7 AF7 AD5 AF1 AD3 AB5 AD28 AD26 AD25 AE26 AH27 AG24 AH24 AJ24 AG22 AH21 AG20 AF19 AJ18 AJ17 AE14 AF13 AG12 AH11 AH16 AE15 AJ9 AE9 AJ7 AH6 AE3 AE2 Ball
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
29
Pinout Table 14. Pinout List (Continued)
Pin Name PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2 PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2 PC3/FCC3_CTS/FCC2_UT8_TXD2/DACK2/CTS4 PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR2/ FCC1_UTM_RXCLAV1 PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/ FCC1_UTM_TXCLAV1 PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3 PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2 AC5 AC4 AB26 AD29 AE29 AE27 AF27 AF24 AJ26 AJ25 AF22 AE21 AF20 AE19 Ball
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 AE18 PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1 PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7 PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/FCC2_UT8_TXD3/CLK8/TOUT4 PC25/FCC2_UT8_TXD2/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/FCC2_UT8_TXD3/CLK2/TOUT1 PC31/CLK1/BRGO1 AH18 AH17 AG16 AF15 AJ15 AH14 AG13 AH12 AJ11 AG10 AE10 AF9 AE8 AJ6 AG2 AF3 AF2 AE1 AD1
30
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Pinout Table 14. Pinout List (Continued)
Pin Name PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2 PD5/FCC1_UT16_TXD3/DONE1 PD6/FCC1_UT16_TXD4/DACK1 AC28 AD27 AF29 Ball
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2 AF28 PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5 PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3 PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4 PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1 PD12/SI1_L1ST2/L1RXDB1 PD13/SI1_L1ST1/L1TXDB1 PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI AG25 AH26 AJ27 AJ23 AG23 AJ22 AE20 AJ20 AG18 AG17
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/S AF16 PICLK PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/FCC1_UTM_TXCLAV3/S AH15 PISEL/BRGO1 PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1 PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/ FCC1_UTM_RXCLAV2 PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN SPARE12 SPARE42 SPARE53 AJ14 AH13 AJ12 AE12 AF10 AG9 AH8 AG7 AE4 AG1 AD4 AD2 AB3 B9 AB1 AE11 U5 AF25
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
31
Pinout Table 14. Pinout List (Continued)
Pin Name SPARE62 THERMAL04 THERMAL14 I/O power V4 AA1 AG4 AG21, AG14, AG8, AJ1, AJ2, AH1, AH2, AG3, AF4, AE5, AC27, Y27, T27, P27, K26, G27, AE25, AF26, AG27, AH28, AH29, AJ28, AJ29, C7, C14, C16, C20, C23, E10, A28, A29, B28, B29, C27, D26, E25, H3, M4, T3, AA4, A1, A2, B1, B2, C3, D4, E5 U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1, Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5 AA5, AF21, AF14, AF8, AE7, AF11, AE17, AE23, AC26, AB25, Y26, V25, T26, R25, P26, M25, K27, H25, G26, D7, D10, D14, D16, D20, D23, C9, E11, E13, E15, E19, E22, B3, G5, H4, K5, M3, P5, T4, Y5, AA2, AC3 Ball
Core Power
Ground
1 2
Only on Rev C.2 silicon. Must be pulled down or left floating. 3 Must be pulled down or left floating. However, if compatibility with HiP4 silicon is required, this pin must be pulled up or left floating. 4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide available at www.motorola.com/semiconductors.
Symbols used in Table 14 are described in Table 15.
Table 15. Symbol Legend
Symbol OVERBAR UTM UTS UT8 UT16 MII Meaning Signals with overbars, such as TA, are active low. Indicates that a signal is part of the UTOPIA master interface. Indicates that a signal is part of the UTOPIA slave interface. Indicates that a signal is part of the 8-bit UTOPIA interface. Indicates that a signal is part of the 16-bit UTOPIA interface. Indicates that a signal is part of the media independent interface.
32
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Package Description
1.5
1.5.1
Package Description
Package Parameters
Table 16. Package Parameters
Parameter Package Outline Interconnects Pitch Value 37.5 x 37.5 mm 480 (29 x 29 ball array) 1.27 mm
The following sections provide the package parameters and mechanical dimensions for the MPC8260.
Package parameters are provided in Table 16. The package type is a 37.5 x 37.5 mm, 480-lead TBGA.
Nominal unmounted package height 1.55 mm
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
33
Package Description
1.5.2
Mechanical Dimensions
Figure 14 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the maximum solder ball diameter, parallel to primary data A. 4. Primary data A and the seating plane are defined by the spherical crowns of the solder balls. Millimeters Dim Min A A1 A2 A3 b D D1 e E E1 1.45 0.60 0.85 0.25 0.65 Max 1.65 0.70 0.95 -- 0.85
37.50 BSC 35.56 REF 1.27 BSC 37.50 BSC 35.56 REF
Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature
34
MPC8260 (HiP3) Hardware Specifications
MOTOROLA
Ordering Information
1.6
Ordering Information
Figure 15 provides an example of the Motorola part numbering nomenclature for the MPC8260. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact your local Motorola sales office.
MPC 826X C ZU XXX X XX
Product Code Die Revision Level (Nn = Major.minor) Core Voltage Device Number Processor Frequency (CPU/CPM/Bus)
Temperature Range
Package (ZU = 480 TBGA)
Figure 15. Motorola Part Number Key
1.7
Document Revision History
Table 17. Document Revision History
Substantive Changes Initial version -- Temporary revisions Corrected the thermal values in Table 3, "Thermal Characteristics." * Revision of Table 5, "Power Dissipation" * Modifications to Figure 8, Table 2,Table 10, Table 11 * Additional revisions to text and figures throughout * Table 7, Table 8, Table 9, and Table 10: revision 0.7 of this document incorrectly included values for 83 MHz. 83 MHz is not supported on the MPC8260. * Table 14: notes added to pins at AE11, AF25, U5, and V4. * Table 14: additional note added to AE11 * Table 14: modified notes to pins AE11 and AF25. * Table 14: added note to pins AA1 and AG4 (Therm0 and Therm1). * Section 1.1, "Features": updated minimum supported core frequency to 133 MHz * Addition of "Note" at bottom of page 5. * Table 13: Note 3.
Table 17 lists significant changes in each revision of this document.
Document Revision 0 0.1 0.2-0.5 0.6 0.7
0.8
0.9 1.0 1.1
MOTOROLA
MPC8260 (HiP3) Hardware Specifications
35
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors DOCUMENT COMMENTS: FAX (512) 933-2625, Attn: RISC Applications Engineering
implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2002
MPC8260EC/D

▲Up To Search▲

Price & Availability of MPC8260ED

	To Download MPC8260ED Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .